The present invention relates to dry etching methods using plasma.
In recent years, to cope with the quest for higher performance of semiconductor devices, a combined technology of high-dielectric-constant (high-k) gate insulating film and a dual metal gate has been developed and put into practical use to resolve a decrease in drive current and an increase in leakage current. As manufacturing methodology according to the technology there are two approaches: a gate-first technique, which is a conventional gate electrode fabrication method, and a gate-last technique.
The gate-last technique is a method having the steps of forming dummy gates made of material such as polycrystalline silicon, filling an interlayer oxide film between the dummy gates after forming a source and a drain, and removing the dummy gates. A metallic material is filled in a trench portion which was formed by removal of the dummy gate; then, the filled metal material is polished by chemical mechanical polishing (CMP) to thereby form a metal gate (see JP-A-2005-19892).
In the gate-last technique just described, a process of removing the dummy gate by dry etching to thereby form a trench is essential. In addition, there is an occasional need that upper edge portions of this trench are rounded when the trench is formed. In other words, it is required from time to time to provide rounded top edge portions (top rounds) to the trench which is formed by removal of the dummy gate.
A method for forming a trench with its upper corners rounded in a surface of semiconductor substrate is disclosed in JP-A-2005-26662.